A dry etching method is conventionally used in order to form a clearance between elements, a contact hole, and a capacitor in a silicon substrate. In the dry etching method, a deep trench is formed in a CZ silicon substrate by using a mixed gas with O2 and Cl2 or HBr. The mixed gas has a high depositional tendency so that a deposition of a sidewall protecting film is faster than the etching of silicon in the conventional method using the mixed gas. Therefore, a speed of the silicon etching is slow. Further, a metallic contamination is caused, since an inner wall of a chamber is corroded by a strong corrosion effect of the mixed gas.
In order to solve this problem, a dry etching method by using mixed gas plasma is suggested. In the method, a mixed gas with a fluorinate gas, e.g., SF6 gas, and an oxygenic gas, e.g., O2 gas, generates plasma. Ions and radicals of S, F, and O are dissociated from the SF6 gas and the O2 gas, and react with a surface of the Si substrate so that SiF and SiO are generated. In the process of the generation of the SiF, the Si etching is promoted. At the same time, an appropriate amount of the SiO is formed as the sidewall protecting film. Therefore, an isotropic etching by the F-radical is reduced so that an anisotropic and fast etching can be performed. Moreover, in the dry etching method, the SiO film layer, which is generated by the reaction of the silicon substrate and the mixed gas plasma with the SF6 gas and the O2 gas, is formed thinly on the inner wall of a chamber so that a generation of a foreign object due to a removal of an attachment is less, and a wet cycle following the dry etching in order to remove a mask can be kept long.
Furthermore, the SiO film layer formed thinly on the inner wall of the chamber prevents a metal contamination generated on a chamber member from scattering toward the Si substrate. Also, a characteristic trouble of a semiconductor device formed on the substrate can be reduced.
In the conventional method using the SF6 gas and the O2 gas, when an etching process is performed in a SOI (Silicon On Insulater) substrate, the anisotropic etching toward a lower oxide film layer 22 deteriorates so that a side etching region 23 is locally generated as shown in FIG. 2. Number 24 shown in FIG. 2 is a mask. In the etching process, there are physical reactions, e.g., a sputtering by applying a RF wave on the substrate, and chemical reactions by the dissociated radicals. In the side etching region 23, the isotropic Si etching is promoted by the chemical reactions with the dissociated radicals. In the etching process of silicon layer 21, Si—F is generated by a reaction with the F-ion and the Si layer 21. A reaction between the Si—F and the O-ion provides a SiO2 layer film as the protecting film on the sidewall of a trench. However, when the etching reaches the lower oxide film layer 22 of the SOI substrate, in which the etching rate is low, the generation of the Si—F is decreased so that the protecting film of SiO2 becomes thin. This is because the etching rate of the lower oxide film layer 22 is low. In contrast, excess F-ions and F-radicals derived from the F-ions due to the decrease in the reaction of the silicon layer 21 promote to form the side etching region 23 of the silicon layer 21 along with the lower oxide film layer 22 of the SOI substrate, in which the SiO2 protecting film is thin.
A conductor or an insulator is embedded in the trench. For example, when the trench is used for separation between elements, an insulating film such as a silicon oxide film is embedded in the trench. However, a hole, i.e., void, is formed in the silicon oxide film due to an incompletion of the embedment when the side etching region 23 exists. The void causes an increase of a leak current and a decrease of a withstand voltage, and therefore, a yielding rate of the semiconductor device is reduced. Accordingly, a prevention of the generation of the side etching region 23 is an important technology for securing the characteristic of the semiconductor device.
In addition, as shown in FIG. 3, a residual needle, i.e., a black silicon 25, is generated on an external portion of a Si wafer 26. The black silicon 25 is broken in a following washing process. A dust of the black silicon 25 is adsorbed on the surface of the semiconductor substrate and contaminates a washing tank. The black silicon 25 causes problems such as a decrease in a yielding rate and a productivity of the semiconductor device.
The black silicon 25 can be eliminated by increasing a ratio of the SF6 gas to the O2 gas compared with a conventional ratio. However, the increase of the SF6/O2 ratio causes a decrease of the sidewall protecting film so that a side etching region 27 is generated just beneath the mask 24, as shown in FIG. 4.
Furthermore, JP-A-8-241885 discloses a method for preventing a generation of a notching, in which a maximum electric potential of an object in a surface treatment process is kept higher than that of plasma. In the method, a pulse power source is provided in place of a conventional sine wave high-frequency power source as a bias power source. A duty ratio of the pulse power source is equal to or less than 5%. Applying a pulse voltage having a rising speed equal to or more than 103 V/μs generates an electric field, in which an electron is accelerated toward a substrate. However, this method cannot solve the above-described problem, in a case where the etching of the trench having a high aspect ratio is performed by using the fluorinate gas and the oxygenic gas.